Thursday, July 15th
Thursday's program is also available with abstracts and side by side with other events.
09:00‑10:00 Session 1
Chair: TBD
Location: AT 2.11
| 09:00 | Sharad Malik (Princeton University, USA) Invited talk: Managing State Explosion through Runtime Verification |
10:30‑12:30 Session 2
Chair: TBD
Location: AT 2.11
| 10:30 | Matthias Raffelsieper and Mohammadreza Mousavi Efficient Verification of Verilog Cell Libraries |
| 11:00 | Yongjian Li, William Hung and Xiaoyu Song Automatically Exploring Structural Symmetry in Symbolic Trajectory Evaluation |
| 11:30 | Divjyot Sethi, Yogesh Mahajan and Sharad Malik Specification and Encoding of Transaction Interaction Properties |
| 12:00 | Malay Ganai and Weihong Li Bang for the Buck: Improvising and Scheduling Verification Engines for Effective Resource Utilization |
14:00‑15:00 Session 3
Chair: TBD
Location: AT 2.11
| 14:00 | Cindy Eisner (IBM Research Lab, Israel) Invited talk: Why Work on Hardware Verification? |
15:30‑17:30 Session 4
Chair: TBD
Location: AT 2.11
| 15:30 | Stefan Kupferschmid, Matthew Lewis, Bernd Becker and Tobias Schubert Incremental Preprocessing Methods for use in BMC |
| 16:00 | Souheib Baarir, Cecile Braunstein, Emmanuelle Encrenaz, Jean-Michel ILIE, Tun Li, Isabelle Mounier, Denis Poitrenaud and Sana Younes Quantifying Robustness by Symbolic Model checking |
| 16:30 | Gianpiero Cabodi, Sergio Nocco and Stefano Quer Benchmarking a Model Checker for algorithmic improvements and tuning for performance |
| 17:00 | Armin Biere Discussion and Presentation of the Results of the 3rd Hardware Model Checking Competition |